Summary of Status Registers 30 Nov 00 The Door/Roof open/close sequencer distributes status bits regarding the positions of the doors, etc. These are reported to the Interlock Status Controller (ISC; aka Dave's box) which interprets them and forwards them to CONTROL. There are 32 status bits divided into 4 8-bit status registers: a, b, c, and d. The following table was taken from the ISC code. The "Msgs" below refer to the messages on the ISC's LCD display. Only the last two bits produce a message in both the 1 state and the 0 state. Status Registers Rising Edge Msg Falling Edge Msg *************** *************** **************** status register a: sa.7 = right door closing Closing R. Door sa.6 = right roof closing Closing R. Roof sa.5 = right door opening Opening R. Door sa.4 = right roof opening Opening R. Roof sa.3 = left door closing Closing L. Door sa.2 = left roof closing Closing L. Roof sa.1 = left door opening Opening L. Door sa.0 = left roof opening Opening L. Roof status register b: sb.7 = right door close limit R. Door Closed sb.6 = right roof close limit R. Roof Closed sb.5 = right door open limit R. Door Opened sb.4 = right roof open limit R. Roof Opened sb.3 = left door close limit L. Door Closed sb.2 = left roof close limit L. Roof Closed sb.1 = left door open limit L. Door Opened sb.0 = left roof open limit L. Roof Opened status register c: sc.7 = right door >5% open R. Door At 5% sc.6 = right roof >5% open R. Roof At 5% ** sc.5 = right door >95% open R. Door At 95% * sc.4 = right roof >95% open R. Roof At 95% sc.3 = left door >5% open L. Door At 5% sc.2 = left roof >5% open L. Roof At 5% ** sc.1 = left door >95% open L. Door At 95% * sc.0 = left roof >95% open L. Roof At 95% status register d: ** sd.7 = right pause Right Paused ** sd.6 = left pause Left Paused ** sd.5 = pumps on Both Pumps On ** sd.4 = pause Paused sd.3 = closing Closing Shelter sd.2 = opening Opening Shelter sd.1 = right pump on Right Pump On Right Pump Off sd.0 = left pump on Left Pump On Left Pump Off * and ** status bits don't work properly (bug in the sequencer code?). ** bits are frozen at 0. The * bits appear to be confused with the ** bit directly above them in the table. I.e., perhaps their erratic behaviour is due to the sc.1 and sc.5 subroutines overwriting the sc.0 and sc.4 values, respectively.